1. Field of the Invention
The present invention relates to a test pattern signal generator for generating test pattern signals for display monitors which employ cathode ray tubes (CRTs) or liquid crystal panels.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a conventional test pattern signal generator. In the figure, symbols 1a through 1h denote latch circuits which set the operational parameters of the display monitor under test, which include the frequency of sync signal, the pulse width of sync signal, and the range of data display area, to corresponding counters 2a through 2h. The counters 2a-2h count dot clocks or horizontal sync pulses, and they produce count-up signals and clear themselves when they have counted the values which were set by the respective latch circuits. Indicated by 3a through 3d are flip-flops which are set and reset in response to the count-up signals from the pairs of the counters 2a-2h thereby to produce a horizontal sync signal, vertical sync signal, horizontal data display range pulse, and vertical data display range pulse.
Next, a typical operation will be explained. FIGS. 2(a)-2(b) are timing charts showing the typical waveforms of the signals of a display monitor, in which FIG. 2(a) is the vertical sync signal, FIG. 2(b) is the horizontal sync signal, FIG. 2(c) is the horizontal sync signal with its time axis being expanded, and FIG. 2(d) is a data signal. These signals are produced by counting a clock signal having a pulse width corresponding to the minimum light spot displayed on the monitor screen, i.e., dot clocks.
The horizontal sync signal shown by FIG. 2(c) in has a period which is the total length a of dot clocks in number, and has a pulse width which is the total length b of dot clocks. The vertical sync signal shown by FIG. 2(a) has a period which is the total length of A horizontal sync pulses, and has a pulse width which is the total length of B horizontal sync pulses.
On the CRT screen of display monitor, the electron beam scans in a swing motion from left to right and from top to bottom as shown in FIG. 3. The vertical sync pulse is located equivalently at the left end of the first scanning line, and the horizontal sync pulse is located equivalently at the left end of each scanning line. A display monitor of this type does not use the whole scanning area enclosed by the 2-dot-and-dash line X for display, but it uses only area enclosed by the dot-and-dash line Y where scanning is stable.
On this account, the data display area is defined in the vertical direction in terms of horizontal scanning lines from the C-th line to D-th line counted from the vertical sync pulse as shown by (a) in FIG. 4, and in the horizontal direction in terms of dot clocks from the c-th clock to the d-th clock connected from the horizontal sync pulse as shown by (b) in FIG. 4.
In the conventional test pattern signal generator, the timing signals having the values A through D and a through d shown in FIGS. 4(a) and 4(b) are produced by means of flip-flops which are set and reset in response to the counter outputs as shown in FIG. 1. Specifically, the counter 2a is set to the number of dot clocks "a" which corresponds to the horizontal sync period provided by the latch circuit 1a, and the counter 2b is set to the number of dot clocks "b" which corresponds to the horizontal sync pulse width provided by the latch circuit 1b.
The counter 2a counts dot clocks, and when it has counted the value "a" which was set by the latch circuit 1a, it produces and delivers a count-up signal to its own reset terminal and the counter 2b and to the set terminal of the flip-flop 3a. The flip-flop 3a is set by the count-up signal, and its output goes high. The counter 2b is cleared by the count-up signal, and it restarts the counting of dot clocks. When the counter 2b has counted the value "b" which was set by the latch circuit 1b, it delivers a reset signal to the flip-flop 3a. The flip-flop 3a is reset by the signal, and its output goes low. Consequently, the flip-flop 3a produces the horizontal sync signal having a period of "a" and a pulse width of "b" shown by FIG.(c).
The counters 2c and 2d operate in the same manner as 2a and 2b in response to the resulting horizontal sync signal, and the associated flip-flop 3b produces the vertical sync signal having a period of "A" and a pulse width of "B" shown by FIG.(a). Similarly, the counters 2e and 2f count dot clocks, causing the flip-flop 3c to produce the horizontal display range pulse, and the counters 2g and 2h count horizontal sync pulses, causing the flip-flop 3d to produce the vertical display range pulse. The counters 2f and 2h also deliver count values as the address signal of the memory which stores data of test patterns to be displayed.
The conventional test pattern signal generator necessitates the latch circuits 1a-1h, counters 2a-2h, and flip-flops 3a-3d for producing the horizontal sync signal, vertical sync signal, horizontal data display range pulse, and vertical data display range pulse, as described above, and because of vast count values each counter, e.g., counter 2a, is formed of three to four IC devices, resulting in an enormous hardware arrangement besides a large-capacity memory for generating test pattern data. This is a problem.